1. Field of the Invention
This invention relates to multilayer thin film (MLTF) structure containing electronic packages such as multi-chip modules (MCM) and, more particularly, to a method for making engineering changes (EC""s) in the electronic structure and/or repairing defective electrical connections in the MLTF structure and to the resulting MLTF structure and electronic component fabricated by the repair method.
2. Description of Related Art
Thin film electronic components offer an attractive packaging solution for high performance and light weight systems such as in computer, telecommunication, military and consumer applications. With the Semiconductor Industry Association (SIA) predicting clock frequencies in the range 200 MHz-1 GHz in the year 2000, the use for thin film packaging will continue to increase. Though thin films offer high density interconnections, the manufacturing process typically produces some number of non-working interconnections due to process induced defects and a resulting low component product output yield. To assure the quality and reliability of the product, the defective interconnections need to be repaired to ensure their functionality, so as to assure a fault free electronic package.
Package interconnections consist of multiple layers of interconnections which are used to interconnect various parts of the system. After all the layers of the MLTF are fabricated, a final test is performed from the top surface of the package to separate defective interconnects from defect-free interconnects to guarantee the functionality of the interconnects and the package. Since a fully functioning package cannot support any defective interconnects, the package must either be thrown away, which is not feasible for thin film packages due to the high cost involved, or the defective interconnects can be repaired. The repair option accordingly represents an attractive solution for thin film packages.
In the past, repair schemes such as Direct Distribution Engineering Change (DDEC) as shown in U.S. Pat. No. 5,243,140 has been used whereby a series of xe2x80x98addxe2x80x99 and xe2x80x98deletexe2x80x99 repair operations have been used on a fixed metal layout on the top surface of the MLTF structure. In general, the repair scheme utilizes two correction pads arranged in an array, at least two direct distribution structures, a signal pad and conductor extending between at least two direct distribution structures.
In U.S. Pat. No. 4,254,445 a module for LSI chips includes an orthogonal array of sets of pads and fan-out metallization for a large number of chips. Running parallel to the sides of the chips and the fan-out area are several parallel prefabricated, thin film engineering change (EC) interconnection lines terminating in pads adjacent to the fan-out. The pads are arranged to permit discretionary connections of the fan-outs to the EC pads with minimal crossovers by means of short fly wires.
U.S. Pat. No. 4,489,364 shows a chip carrying module including a number of EC change lines buried below the surface of the module. The EC lines are interrupted periodically to provide a set of vias extending up to the upper surface of the module between each set of chips where the vias are connected by dumbbell-shaped pads including a narrow link which permits laser deletion. The fan-out pads can be connected to the pads by means of fly-wires.
U.S. Pat. Nos. 5,220,490 and 5,224,022 show custom interconnections done by personalizing (not repairing) the top metal wiring. The customizable circuit has a high density of orthogonally placed X and Y conductors capable of interconnecting closely spaced LSI circuits.
The above patents are incorporated herein by reference.
A typical thin film structure containing a number of interconnections using vias, pads and connecting conductor straps is shown in cross-section FIG. 1 as numeral 10. The structure is typically mounted on a substrate (not shown) such as a ceramic material (MCM-D/C) containing wiring. The MLTF structure consists of a power plane (brick) or capture level 19, mesh 1 level 11, X wiring layer 12, Y wiring layer 13, ground plane mesh 2 layer 14 and a top surface metallurgy level (TSM) 15. The top surface metallurgy (TSM) level contains the vias 16, corresponding pads 17 and via-pad strap connectors 18 for connecting chips to the thin film package. The top surface metallurgy level would also contain the repair wires for correcting faulty interconnections or making EC""s as discussed hereinbelow.
FIG. 2, which represents a partial top view of a typical MCM and of the TSM metallization level 15 of FIG. 1 shows one chip area bounded by the dotted lines 27, vias 16 and chip connection pads 17 (such as controlled collapse chip connection pads known as C4 pads) with the vias representing connections to the I/O in the MLTF structure and supporting substrate if any and the C4 pads represent the microsockets supporting the C4 balls connecting the chip to the thin film substrate. As can be seen from the figure, the C4 pads 17 are offset from the vias 16, which is preferable in high performance machines to ensure the elimination of any discontinuities which may arise due to the presence of the faulty interconnection still connected to the repaired wire. In the figure, the C4 pads are connected to the vias by conductor straps 18 that provide the connection for non-faulty interconnections. The strap is conventionally created by a mask during the fabrication of the TSM and if the interconnection is faulty, a laser delete operation is necessary to disconnect the faulty interconnection from the C4 pad. As will be more fully discussed hereinbelow, vias 16a and 16b were found to be part of defective interconnections and are not to be used. Corresponding pads 17a and 17b are shown connected to repair lines 30R and 30Rxe2x80x2 by straps 18R and 18Rxe2x80x2, respectively.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for repairing interconnections and/or making engineering changes in multilayer thin film containing electronic components such as MCM""s.
Another object of the invention is to provide a method for repairing interconnections and/or making EC""s in multilayer thin containing film electronic components employed on top of ceramic, laminate, dielectric or other substrates.
A further object of the invention is to provide a MLTF structure having repair lines and/or EC lines made using the method of the invention.
A still further object of the invention is to provide a multi-chip module containing a MLTF structure having repair lines and/or EC lines made using the method of the invention.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects, which will be apparent to those skilled in the art, are achieved by the present invention which relates to a method for repairing interconnections in multilayer thin film (MLTF) structures typically used to make multi-chip modules (MCM) by employing the MLTF structure on MCM""s such as MCM-C (ceramic substrate), MCM-D (non-conductive substrate) and MCL-L (laminate substrate) comprising making the MLTF layer by layer up to a layer adjacent the top surface layer, determining the interconnection defects at the thin film layer below and adjacent to the top surface layer of the MLTF structure, defining the top surface connections needed to repair the defective interconnections based on the defects uncovered and/or EC""s desired, preferably using a computerized algorithm to determine the best metal line routes on the top surface layer, defining by a photoresist technique the top surface layer to form the top surface metallization and a plurality of orthogonal X-Y repair lines and then connecting pads of vias needing repair by metal connecting line straps to an X repair line and/or a Y repair line and then connecting the connected X and/or Y repair line to the desired pad by metal connecting line straps by exposing the photoresist layer based on the defects uncovered and/or EC changes desired to define the desired metal connecting lines and then developing and plating the top surface metallization layer.
Broadly stated, after the MLTF has been formed to the thin film layer adjacent to and below the TSM layer, electrical testing is performed to determine any faulty interconnections. The interconnection faults may arise due to opens or shorts in the wiring. Simple capacitance testing or other such testing methods can be used to differentiate between the defective and defect-free interconnections. It is important to note that any opens in an input/output (I/O) net or power-ground plane short is a fatal defect and cannot be repaired. Next the top surface metallurgy level is built similarly by applying a polyimide or similar dielectric material having defined vias, applying a metal conducting layer, applying a photoresist layer and using, for example, a fixed mask to define the C4 pads, via capture pads, a plurality of orthogonal X-Y conductor lines preferably positioned both within and outside the chip footprint area and running between the chip areas, and conducting straps connecting the pads to the via locations. Defective interconnections are preferably isolated so that there is no conductor strap between the pad and corresponding defective via interconnection. Using the determined interconnection data, the straps needed on the top surface to repair the component by connecting pads of defective vias to other pads are defined using a phototool to expose the metal line repair straps and then the photoresist is developed and the complete top surface metallurgy plated.
For each defect and/or engineering change made, the repair line from the xe2x80x9cdefectivexe2x80x9d pad to the repair location, is a first repair strap to an X line and/or Y line and is a single (individual) conductive line used to repair each defective via or to make each engineering change. A second repair strap is then needed to connect from the first repair strap connected X line and/or Y line to the desired pad. X repair lines and Y repair lines are then interconnected in a similar fashion by using a phototool to reform the circuit path or connect the xe2x80x9cdefectivexe2x80x9d pad to the desired repair pad. The photoresist is then developed and the complete top surface metallurgy plated.
In another aspect of the invention, the proposed method of the invention can also be used for implementing engineering changes (EC""s). EC""s are required in a product to make changes at the systems level. In this method, EC""s can be incorporated by using some of the C4 pads primarily for ECs with an EC wire buried in the substrate and connected to the C4 pad. The repair scheme can be used to disconnect or delete the straps between the via and the C4 pad of the original connection, and exposing a strap to an X line and/or Y line for developing and metallization which repair strap would then be connected to the defined EC C4 pad as described hereinabove. EC""s are described and shown in U.S. Pat. No. 5,243,140, supra.